Digital Components Mcqs
Our Collection of Digital Components multiple choice questions and answers focuses on all areas of Digital Components covering a collection of most authoritative and best reference books on Digital Components. One should spend 1 hour daily for 2-3 months to learn and assimilate Digital Components comprehensively.
32. How many flip flops are required to construct a decade counter
10
3
4
2
33. Which TTL logic gate is used for wired ANDing
Open collector output
Totem Pole
Tri state output
ECL gates
Answer & Solution
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34. The MSI chip 7474 is
Dual edge triggered JK flip-flop (TTL)
Dual edge triggered D flip-flop (CMOS)
Dual edge triggered D flip-flop (TTL)
Dual edge triggered JK flip-flop (CMOS)
Answer & Solution
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35. When the set of input data to an even parity generator is 0111, the output will be
1
0
Unpredictable
Depends on the previous input
36. How many flip-flops are required to construct mod 30 counter
5
6
4
8
37. The number of control lines for 16 to 1 multiplexer is
2
4
3
5
38. The number of control lines for 32 to 1 multiplexer is
4
5
16
6
39. The logic 0 level of a CMOS logic device is approximately
1.2 volts
0.4 volts
5 volts
0 volts
40. How many select lines will a 32:1 multiplexer will have
5
8
9
11
41. Which of following consume minimum power?
TTL
CMOS
DTL
RTL
42. ABCD – seven segment decoder / driver in connected to an LED display. Which segments are illuminated for the input code DCBA = 0001.
B, c
C, b
A, b, c
A, b, c, d
43. How many flip-flops are required to produce a divide-by-32 device?
4
6
5
7
44. A demultiplexer can be used as
Encoder
Decoder
Multiplexer
None of the above
45. If the clock input applied to a cascaded Mod-6 & Mod-4 counter is 48KHz. Than the output of the cascaded arrangement shall be of
4.8 KHz
12 KHz
2 KHz
8 KHz